CHEN Shou-zhi, WANG Xiao-li, ZHANG Xian-rao. A Low Power DFT Technology Based on EDT[J]. Microelectronics & Computer, 2013, 30(11): 159-164.
Citation: CHEN Shou-zhi, WANG Xiao-li, ZHANG Xian-rao. A Low Power DFT Technology Based on EDT[J]. Microelectronics & Computer, 2013, 30(11): 159-164.

A Low Power DFT Technology Based on EDT

  • This paper presents a low power DFT technology based on EDT,and introduces an optimization method when setting power threshold.This low power DFT technology has the ability to reduce WSA during testing by filling 0 to test patterns,which optimizes WSA from 31.55% to 25.12%.Otherwise,setting power threshold can reduce peak testing power,which optimizes LST to 49.76% to 21.21%,RST from 45.73% to 25.00%.Coverage drop,caused by power threshold,could be improved by reducing the scan chains length.
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