An Area-Efficient Design of RS(255,223) Decoder for 10G EPON

This paper presents a new area-efficient implementation for Reed-solomon(RS) decoder.By using modified euclidean arithmetic to implement the equation solving circuits and the folding architecture for other modules,this method has decreased GF multipliers and simplify the hardware structure.Based on the TSMC 90nm standard cell library,the proposed RS decoder consists of about 24000 gates,which is about 36% smaller than the same kind of conventional ones.