An Algorithm of Interpolation Filter Based on Parallel Processing Technology and Its FPGA Implementation

The performance of interpolation filter has a direct impact on the bit error rate of all digital receiver. It is the key to all-digital receiver that design a good performance of the interpolation filter. The analysis and research are based on the existing Farrow structure of Lagrange interpolation filter. The parallel processing technology are used to improve the speed of filter. We have simulated and realized the structures for FPGA. The results show that the structure has faster operational rate and lower energy consumption.